1. Field of the Invention
The present invention relates to a display device, and more particularly to a display device which mounts a semiconductor chip on a substrate thereof.
2. Description of the Related Art
For example, a liquid crystal display device is configured such that a display part of the liquid crystal display device includes a pair of substrates which is arranged to face each other in an opposed manner with liquid crystal interposed therebetween, one substrate out of the respective substrates extends to a region other than the display part (a peripheral portion), and a semiconductor chip which is formed of a liquid crystal display drive circuit is mounted on an extending portion of one substrate.
On a surface of the substrate on which the semiconductor chip is mounted, a plurality of line layers for inputting signals into respective pixels within the display part is formed, wherein the semiconductor chip is mounted on the surface of the substrate by face-down bonding such that respective bump electrodes of the semiconductor chip are connected to terminals of the respective corresponding line layers.
Further, in such a constitution, recently, the number of pixels in the display part is increased and, along with the increase of the number of pixels, the number of line layers which input signals into the respective pixels is increased.
Accordingly, not to mention that it is necessary to form the respective line layers with a small parallel pitch within a region where the semiconductor chip is mounted, it is also necessary to form the respective terminals in a further concentrated pattern.
Here, as one method for forming the respective terminals in a concentrated pattern, for example, as disclosed in the following patent document 1, there has been known a method in which a group of terminals which are constituted of terminals arranged in the parallel direction of the respective line layers are arranged at two stages in the extending direction of the respective line layers, wherein the respective line layers which are arranged for every one other line are connected to the respective terminals of the group of terminals at the first stage, and another remaining respective line layers are connected to the respective terminals of the group of terminals at the second stage. Alternatively, as disclosed in the following patent document 2 which share the substantially same technical concept as patent document 1, there has been known a method which further uses a group of terminals on a third stage.
Here, in the above-mentioned methods, a semiconductor chip is also, to establish the connection thereof with the terminals, constituted of a group of bump electrodes at two stages or a group of bump electrodes at three stages.    Patent Document 1: JP-A-2005-99310    Patent Document 2: JP-A-8-313925